DTMF circuit working with all mobile phones

Hello friends, this is my first update on my blog. Here I'm representing the circuit for the DTMF circuit which is working with all the mobile phones. Any ordinary circuit will support only few nokia and some phones but doesn't support the touch screen phones. This circuit will help you to work with all touch screen phones, android phones etc. Here I'm using the CM8870 as DTMF decoder. SL1 is a connector for +5V power supply. And X1 is the 3.5mm audio Jack for connecting the 3.5mm male to male cable in order to reduce the hectic work for cutting the wires.

Component Table is given here:

• R1          =    10K
• R2          =    330K
• R3, R4   =    100K
• R5, R6   =    62K
• R7         =    1000K
• R8         =    220 Ohm
• Q1        =     3.5795MHz
• C2,C3   =    0.1 Micro-farad

You can check the data sheet of CM8870 for the pin details and other features of the DTMF decoder.  Pin configuration of MT8870 is given below:

Pin details of tis IC is given below:

1	IN+	Non-Inverting Op-Amp (Input).
2	IN-	Inverting Op-Amp (Input).
3	GS	Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor.
4	V Ref	Reference Voltage (Output). Nominally V   /2 is used to bias inputs at mid-rail.
5	INH	Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down.
6	PWDN	Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down.
7	OSC1	Clock (Input).
8	OSC2	Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit.
9	V SS	Ground (Input) . 0V typical.
10	TOE	Three State Output Enable (Input). Logic high enables the outputs Q1 -Q4. This pin is pulled up internally.
11- 14	Q1 -Q4	Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance.
15	StD	Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt.
16	ESt	Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17	St/GT	Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18	V DD	Positive power supply (Input) . +5V typical.